1. Field of the Invention
The present invention relates to a system and a method of analysis, processing, observation of LSI having a built-in memory unit.
2. Description of the Related Art
Minute observation of a defective part of LSI by means of a scanning electron microscope, observation of a LSI section after cutting the LSI by means of a focusing ion beam (FIB), and composition analysis of the LSI by using a method such as electron beam probe microanalysis (EPMA) have hitherto been performed to clarify causes of defects in wafer surfaces produced during production of the memory LSI.
For performing observation or composition analysis of a defective part of LSI, it is necessary to indicate a spot to be observed with coordinates calculated from an origin fixed in a wafer surface. As a judgment standard for designating a part as a defective part to be observed is the state of the part is divided into two types in a broad way. The first type is a part detected as abnormal in shape by using an optical visual inspection device, and the second type is a part found electrically defective in function by a tester.
Specifying a part as abnormal in shape by using an optical visual inspection device is conducted, for example, by using a wafer visual inspection device of KLA co. ltd., USA, that is, model KLA21 xx series. With this model, a part of abnormal shape is specified by selecting one corner of a LSI chip disposed nearly in the center of a wafer surface as an origin, shifting the wafer or a stage mounted with the wafer to calculate a distance from the origin to the part of the abnormal shape.
A part of inferior electrical function of LSI found by a tester is designated by using memory cells regularly arranged in memory LSI. Normally, designation of memory cells is performed by using a logical address which is coordinates on a circuit diagram different from the circuit diagram of a physical address which designates the relative disposition in the wafer surface and by designating the number of the data input/output terminal which is called I/O.
When a test result of a part of an inferior electrical function by a tester is specified with the logical address, it is considered necessary to convert the data from the logical address to the physical address inthewafersurfaceand further transform to real array coordinates for specifying the part of electrically inferior part, and after finishing this, it becomes possible for the first time to perform composition analysis or various kinds of observations.
Conversion from the logical address to the physical address is performed by using a scramble function. The scramble function is constituted by any one or a combination of logical operators which use the logical address or I/O number as input, such as NOT (or INV which means inversion), AND, OR, NAND, NOR, XOR, XNOR, BUFFER (this means no processing is applied to input), the combination being different depending on kinds of LSI to be combined. Since the physical address expresses relative position coordinates between cells, it is possible to clearly indicate real arrangement coordinates of the defective cell by multiplying the physical address by a cell dimension and adding a dimension of wiring to be inserted between cells, a dimension of a peripheral circuit and a distance from the coordinate origin of the real array on memory LSI to the origin of the physical address.
A bit map display is used as means to find defects distribution by expressing parts of inferior electrical function detected by a tester in a distribution chart prepared with reference to a wafer surface. In this display, the physical address corresponding to the defective cell in the memory is expressed as a point on the coordinates, the point being printed on a paper in one case or displayed on a screen of such as a work station in another.
In the above case, a part of an electrically inferior function is specified by such as the above tester, the logical address is converted to the physical address by using the scramble function to find a distance in the wafer surface measured from the known origin, and the wafer or a stage on which the wafer is mounted is shifted by a desired distance from the origin to perform analysis or various kinds of observation.
Of the prior technique described above, a technique for specifying a part of abnormal shape by using an optical visual inspection device instructs that the wafer or a stage on which the wafer is mounted is shifted by a desired distance from the origin to perform analysis or various kinds of observation. However, when the accuracy of a stage shifting mechanism or a distance measuring mechanism is poor compared with the position accuracy which is required for indicating a defective part, analysis or observation is performed on a part different from the real defective part, thereby missing the chance to precisely find the real cause of defects.
The above problem similarly occurs when analysis or observation of a defective part is performed after the defective part is designated by using a tester. As a result of an electrical test, a defective cell can be specified from the address of a defect and a distance of the defective cell from the origin can be calculated by reading a dimension of a memory LSI chip or a dimension of the cell from design information. However, correct analysis or various kinds of observation of the defective cell is impossible if the stage traveling accuracy is relatively low. For example, a cell dimension of 16 Mbit dynamic random access memory (hereinafter referred to as DRAM) LSI is less than 1 .mu.m, while traveling accuracy of the present stage is about 1 .mu.m. As the LSI grows larger being more highly integrated to such as 64 Mbit or 256 Mbit, the cell dimension becomes still smaller than the stage traveling accuracy.
When a value, which is obtained by integrating the number of memory LSI included between the origin and a defective cell on a memory LSI wafer, is multiplied by a dimension of memory LSI or by a cell dimension to calculate a distance, the error included in the dimension of the memory LSI or the cell becomes enlarged by the number of integration.
When a bit map display, in which a physical address corresponding to a defective cell in the memory is expressed as a point on the coordinates, is used, the bit map display calculates a position of a cell which corresponds to a defective address even when the cause of the defect is not in the cell but in the peripheral circuit which drives the cell. Therefore, there is a problem that it can not clarify through analysis, processing and observation of the LSI whether the cause of the defect is in the cell or in the peripheral circuit.
When the cause of a defect is in the peripheral circuit which drives a cell, it is necessary to make correction of the position and dimension from those of a defective cell to the peripheral circuit which drives the cell before performing analysis, processing and observation of the defective cell. This correction must be made after judging the state of the defect depending on the result of an electrical test. Further, since the position information of the peripheral circuit which is to be corrected is different for each kind of memory LSI, there occur problems such that it is difficult to perform the job well unless an engineer is well versed in circuit design information and layout design information, and further correction itself will take much time to go through.